Questneers : Changhwan Shin (Korea University), Chul-Ho Lee (Seoul National University)
As semiconductor process technology has reached single-digit nanometer sizes, silicon-based semiconductor process technology has reached its limits. Despite efforts such as structural changes and new material development to overcome these limits, many new technologies are experiencing difficulties in realization. What are the difficulties in developing angstrom (Å)-scale semiconductor manufacturing process technology smaller than nano units, and what efforts are needed to accelerate the development of future advanced industries?
News articles about Samsung and TSMC planning to start mass production of 2-nanometer (nm) processes in 2025 make it easy to encounter news about ultra-fine integration process technology in single-digit nanometer units recently. Semiconductor technology has developed performance by integrating more semiconductor devices on chips through process miniaturization. This miniaturization is looking toward angstrom units, which are similar in scale to the diameter of a single atom, beyond nanometer units. However, various technical difficulties lie ahead.
The history of semiconductors began with the invention of the metal-oxide-semiconductor field-effect transistor (MOSFET) in 1959. Since then, based on silicon (Si)-based complementary metal-oxide-semiconductor (CMOS) process technology, it has developed for 50 years by doubling integration density every 1-2 years according to Moore’s Law. However, silicon-based CMOS processes are showing limitations in miniaturization. Since the introduction of 14-nanometer FinFET processes, new forms of design such as Gate All-Around (GAA) nanowires and nanosheets are being promoted to realize even more miniaturized processes. Also, as top-down processes by photolithography reach limits at the nanometer scale, efforts are being made to continuously increase CMOS process integration density by pursuing horizontal miniaturization in angstrom-scale XY axes along with vertical three-dimensional integration in the Z axis.
There are several challenges to be solved to implement angstrom-scale CMOS processes, which are one-tenth of a nanometer. For reference, angstrom-scale here does not mean fine linewidth but refers to process technology nodes after (below?) 1 nanometer. First, with current trends in lithography equipment technology development, it is difficult to implement angstrom-scale CMOS processes. Second, as circuit linewidth becomes finer, leakage current phenomena increase, and current silicon materials are not suitable for preventing this. That is, new channel materials are essential for angstrom-level miniaturization. Third, since the existing silicon-based infrastructure built over half a century in the semiconductor industry is massive, there are cost advantages from economies of scale and depreciation. In this situation, it is difficult for new processes reflecting new materials and designs to have competitive advantages. Therefore, new materials and technologies capable of angstrom-scale processes must be compatible with existing silicon-based CMOS processes. These challenges are very difficult problems to find answers to.
Research related to this is being actively conducted. First, as a method to increase chip integration density through vertical integration rather than horizontal miniaturization that has reached limits, hybrid bonding technology is being developed where heterogeneous materials are bonded together on wafer surfaces. Ultimately, research is underway to achieve new performance and functions through Monolithic 3D Integration where multiple layers are sequentially stacked.
Also, to overcome the limitations of silicon materials themselves, research is being actively conducted to use new semiconductor materials such as two-dimensional channel materials with angstrom-scale thickness. However, in this case, compatibility with existing CMOS processes becomes a problem. That is, as part of bottom-up approaches seeking to design devices at atomic or molecular levels, despite much research on 1- and 2-dimensional materials such as carbon nanotubes (CNT) and graphene over the past 20 years, the industry has been unable to decide on new technology investments because they are not compatible with existing CMOS processes. Therefore, research to secure contact points with mature CMOS processes is desperately needed in this direction of research. Also, in bottom-up approaches, technology to simultaneously form complementary N-type and P-type two-dimensional materials is essential for implementing integrated circuits, but the carrier mobility of P-type two-dimensional semiconductors is relatively lower than N-type, making it difficult to achieve high performance. Research on P-type two-dimensional semiconductors to overcome this problem is very insufficient. From a hybrid bonding perspective, combining silicon-based CMOS with N-type and P-type two-dimensional semiconductors could be a viable solution, but much research is needed for realization.
If hybrid bonding technology between two-dimensional semiconductors and silicon-based CMOS can be created, angstrom-scale CMOS integration processes superior to existing ones in terms of Performance, Power, Area, and Cost (PPAC) could be realized. If this technology becomes possible, development in various technology areas such as artificial intelligence, autonomous vehicles, and high-performance computing will be promoted, and particularly since energy efficiency can be improved, power consumption and cooling costs of AI and data centers, which have recently emerged as environmental problems, will be greatly improved.
Looking back on research and development experience, proposing new topics does not always receive praise and applause. To break existing frameworks with ideas that will amaze the world and persuade people requires tremendous pain as much as the expression “sensational.” However, if philosophy and vision are clearly established and one becomes immersed, (people) will look more seriously once more, and (this) will help overcome the world’s inertia.