Can we break through the fundamental limitations of silicon-based technology and create new semiconductor devices that can be harmonized with existing semiconductor platforms?

The devices currently used in the semiconductor industry are transistors using silicon-based complementary metal oxide semiconductor (CMOS) technology. To date, silicon is the only material that can create these CMOS structures on a large scale. Under the silicon-based paradigm, following Moore’s Law, development has proceeded rapidly by doubling the number of transistors in integrated circuits every 18 months. Recently, technology has reached the level where tens of billions of transistors can be integrated on a single chip. This technological development has been achieved through making transistors smaller, that is, through downsizing. Until the early 2000s, transistors had linewidths (nodes) of about 100nm, but the introduction of High-K metal gate processes enabled 45nm processes, and the introduction of Fin Field-Effect transistor structures enabled processes of 22nm and below. Currently, Samsung Electronics and TSMC have developed technologies down to 3nm and below. However, transistor downsizing is expected to reach its limits soon. The problem of leakage current becomes more serious as nodes become smaller, and above all, the physical limit size for distinguishing unit bits (0/1) at room temperature is given as 1.5nm. With the rapid increase in computational requirements due to artificial intelligence development and the demand for energy-efficient devices that operate at low power, downsizing transistors alone can no longer be a fundamental solution to the problem. To overcome this, the following directions are currently being attempted.

First, new device technologies such as NC-FET and tunneling-FET are being attempted as new device technologies to compensate for the limitations of silicon-based CMOS-FET. Although these technologies will play important roles in implementing sub-3nm devices, they fundamentally share the limitations of silicon-based field-effect transistors. Second, much research is being conducted to utilize two-dimensional semiconductor materials such as transition metal dichalcogenides (TMD) to overcome the disadvantages of ultra-small silicon transistors. Two-dimensional semiconductors can stably reduce channels down to the size of a single crystal layer and avoid short channel effects, making them advantageous for 1nm-class device technology. However, even when using two-dimensional semiconductor materials, the excessive energy consumption problems and physical linewidth limitations of CMOS technology remain the same.

Various accelerating technologies and packaging technologies will be developed and applied based on these technologies to increase computing efficiency. However, these CMOS-based device technologies inevitably face the fundamental physical limit of 1.5nm. Therefore, to break through this limit, we must consider completely new device technologies that depart from the existing paradigm, such as new device technologies that overcome von Neumann architecture (non von Neumann architecture). These alternative device technologies must satisfy the conditions of dramatically low energy consumption and the ability to perform ultra-high-performance computations. Most importantly, the device technologies that will implement these new computing architectures must be able to be transplanted onto the platforms of the existing accumulated semiconductor industry without major strain.

The following alternatives can be considered as new device technologies beyond silicon. First, there is the memristor device that enables computation of large amounts of data at low power, departing from CMOS technology. Memristors have a metal-insulator-metal junction structure and, unlike transistors, operate as two-terminal devices rather than three-terminal devices, and have the advantage of multi-layer information processing. Because they are advantageous for high integration and operate at low power, much research is being conducted to introduce them to neuromorphic computing suitable for artificial intelligence computation. However, devices that implement multi-layered resistance values with high reproducibility and reliability that can stably implement multi-layer information processing have not yet been created. Second, as a more futuristic technological possibility, we can consider technologies that use states where two electrons combine to conduct without resistance, such as superconducting pairs or excitons, but these have not yet developed into devices that can perform specific calculations. Third, there could be technologies using materials that are topological insulators with topological conduction channels that allow conduction without resistance. In this alternative case as well, technology for utilizing them as devices capable of multi-layer information processing must be additionally developed. Fourth is technology using soliton particles that are topologically protected and conduct without resistance, which has recently been demonstrated to be implementable in silicon and 2D materials. Soliton devices have sufficient potential as ultra-low power, ultra-high performance devices because they have no energy consumption due to resistive heating and can perform multi-base arithmetic operations.

As discussed above, current silicon device technology will continue to develop by downsizing 3nm-class device technology and will eventually reach the physical limit size of 1.5nm. For this, in the short to medium term, the current development trend will be extended through partial material improvements using 2D materials such as TMD. However, after reaching the physical limit of 1.5nm, computing architectures that go beyond von Neumann computing and post-FET device technologies that support them will be absolutely required to implement ultra-low power, ultra-high performance computing. Device technologies to support new computing such as neuromorphic computing must implement multi-layer information processing such as multi-base arithmetic operations with very low power consumption, and memristors, exciton devices, soliton devices, etc. are emerging as these challenges. However, there are still many technical difficulties to overcome, and particularly, methods for harmonious integration into existing silicon-based semiconductor platforms are not being presented. This is the grand quest of semiconductor device technology that we face.